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november 2006 rev 1 1/36 36 viper53 - e off-line primary switch features switching frequency up to 300khz current limitation current mode control with adjustable limitation soft start and shut-down control automatic burst mode in standby condition (?blue angel? compliant ) undervoltage lockout with hysteresis high voltage star-tup current source overtemperature protection overload and short-circuit control description the VIPER53-E combines an enhanced current mode pwm controller with a high voltage mdmesh power mosfet in the same package. typical applications cover offline power supplies with a secondary power capability ranging up to 30w in wide range input voltage, or 50w in single european voltage range and dip-8 package, with the following benefits: overload and short circuit controlled by feedback monitoring and delayed device reset. efficient standby mode by enhanced pulse skipping. primary regulation or secondary loop failure protection through high gain error amplifier. general features type european (195 - 265vac) us / wide range (85 - 265 vac) dip-8 50w 30w powerso-10 tm 65w 40w dip-8 powerso-10 www.st.com block diagram ff oscillator 150/400ns blanking 1v 4v overtemp. detector 8.4/ 11.5v 15v 0.5v vdd osc drain tovl comp source pwm latch on/off blanking time selection pwm comparator current amplifier s r1 r2 r3 r4 r5 q 8v 4.35v overload co mparato r 18v 4.5v 125k 0.5v standby co mparato r overvoltage comparato r error amplifier uvlo comparato r h comp
contents viper53 - e 2/36 contents 1 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin connections and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 operation pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 primary regulation configuration example . . . . . . . . . . . . . . . . . . . . . . 15 6 secondary feedback confi guration example . . . . . . . . . . . . . . . . . . . . 17 7 current mode topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 high voltage start-up current source . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10 short-circuit and overload prot ection . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11 transconductance error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12 special recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 13 software implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 14 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
viper53 - e electrical data 3/36 1 electrical data 1.1 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. 1.2 thermal data table 1. absolute maximum rating symbol parameter value unit v ds continuous drain source voltage (t j = 25 ... 125c) (1) -0.3 ... 620 v i d continuous drain current internally limited a v dd supply voltage 0 ... 19 v v osc osc input voltage range 0 ... v dd v i comp i tovl comp and tovl input current range (1) 1. in order to improve the ruggedness of the device ve rsus eventual drain overvo ltages, a resistance of 1k ? should be inserted in series with the tovl pin.\ -2 ... 2 ma v esd electrostatic discharge: machine model (r = 0 ? ; c = 200pf) charged device model 200 1.5 v kv t j junction operating temperature internally limited c t c case operating temperature -40 to 150 c t stg storage temperature -55 to 150 c table 2. thermal data symbol parameter powerso-10 (1) 1. when mounted on a standard single-sided fr4 board wi th 50mm2 of cu (at least 35 mm thick) connected to the drain pin. dip-8 (2) 2. when mounted on a standard single-sided fr4 board wi th 50mm2 of cu (at least 35 mm thick) connected to the device tab. unit r thjc thermal resistance junction-case max 2 20 c/w r thja thermal resistance ambient-case max 60 80 c/w
electrical characteristics viper53 - e 4/36 2 electrical characteristics t j = 25c, v dd = 13v, unless otherwise specified table 3. power section symbol parameter test conditions min. typ. max. unit bv dss drain-source voltage i d = 1ma; v comp = 0v 620 v i dss off state drain current v ds = 500v; v comp = 0v; t j = 125c 150 a r ds(on) static drain-source on state resistance i d = 1a; v comp = 4.5v; v tovl = 0v t j = 25c t j = 100c 0.9 1 1.7 ? ? t fv fall time i d = 0.2a; v in = 300v (1) 1. on clamped inductive load 100 ns t rv rise time i d = 1a; v in = 300v (1) 50 ns c oss drain capacitance v ds = 25v 170 pf c eon effective output capacitance 200v < v dson < 400v (2) 2. this parameter can be used to compute the energy dissipated at turn on e ton according to the initial drain to source voltage v dson and the following formula: 60 pf table 4. oscillator section symbol parameter test conditions min. typ. max. unit f osc1 oscillator frequency initial accuracy r t = 8k ? ; c t = 2.2nf figure 12 on page 12 95 100 105 khz f osc2 oscillator frequency total variation r t = 8k ? ; c t = 2.2nf figure 16 on page 14 v dd = v ddon ... v ddovp ; t j = 0 ... 100c 93 100 107 khz v oschi oscillator peak voltage 9v v osclo oscillator valley voltage 4v e ton 1 2 -- - c eon 300 2 v dson 300 ---------------- ?? ?? 1.5 ??? =
viper53 - e electrical characteristics 5/36 table 5. supply section symbol parameter test conditions min. typ. max. unit v dsstart drain voltage starting threshold v dd = 5v; i dd = 0ma 34 50 v i ddch1 startup charging current v dd = 0 ... 5v; v ds = 100v figure 5 on page 10 -12 ma i ddch2 startup charging current v dd = 10v; v ds = 100v figure 5. -2 ma i ddchoff startup charging current in thermal shutdown v dd = 5v; v ds = 100v figure 7. t j > t sd - t hyst 0ma i dd0 operating supply current not switching f sw = 0khz; v comp = 0v 811ma i dd1 operating supply current switching f sw = 100khz 9ma v ddoff v dd undervoltage shutdown threshold figure 5 on page 10 7.5 8.4 9.3 v v ddon v dd startup threshold figure 5. 10.2 11.5 12.8 v v ddhyst v dd threshold hysteresis figure 5. 2.6 3.1 v v ddovp v dd overvoltage shutdown threshold figure 5. 17 18 19 v table 6. error amplifier section symbol parameter test conditions min. typ. max. unit v ddreg v dd regulation point i comp = 0ma figure 11. on page 11 14.5 15 15.5 v ? v ddreg v dd regulation point total variation i comp = 0ma; t j = 0 ... 100c 2 % g bw unity gain bandwidth from input = v dd to output = v comp i comp = 0ma figure 14 and 15 700 khz av ol voltage gain i comp = 0ma figure 14 and 15 40 45 db g m dc transconductance v comp = 2.5v figure 11. 11.41.8ms v complo output low level i comp = -0.4ma; v dd = 16v 0.2 v v comphi output high level i comp = 0.4ma; v dd =14v (1) 1. in order to insure a correct stability of the error am plifier, a capacitor of 10nf (minimum value: 8nf) should always be present on the comp pin. 4.5 v i complo output sinking current v comp = 2.5v; v dd = 16v figure 11. on page 11 -0.6 ma i comphi output sourcing current v comp = 2.5v; v dd = 14v figure 11. 0.6 ma
electrical characteristics viper53 - e 6/36 table 9. over temperature protection section table 7. pwm comparator section symbol parameter test conditions min. typ. max. unit h comp ? v comp / ? i dpeak v comp = 1 ... 4 v figure 10. di d /dt = 0 1.7 2 2.3 v/a v compos v comp offset di d /dt = 0 figure 10. on page 11 0.5 v i dlim peak drain current limitation i comp = 0ma; v tovl = 0v figure 10. di d /dt = 0 1.7 2 2.3 a i dmax drain current capability v comp = v compovl ; v tovl = 0v di d /dt = 0 1.6 1.9 2.3 a t d current sense delay to turn-off i d = 1a 250 ns v compbl v comp blanking time change threshold figure 6 on page 10 1v t b1 blanking time v comp < v compbl figure 6. 300 400 500 ns t b2 blanking time v comp > v compbl figure 6. 100 150 200 ns t onmin1 minimum on time v comp < v compbl 450 600 750 ns t onmin2 minimum on time v comp > v compbl 250 350 450 ns v compoff v comp shutdown threshold figure 9 on page 11 0.5 v table 8. overload protection section symbol parameter test conditions min. typ. max. unit v compovl v comp overload threshold i tovl = 0ma (1) figure 4 on page 9 1. v compovl is always lower than v comphi 4.35 v v diffovl v comphi to v compovl voltage difference v dd = v ddoff ... v ddreg ; i tovl = 0ma figure 4. (1) 50 150 250 mv v ovlth v tovl overload threshold figure 4. 4v t ovl overload delay c ovl = 100nf figure 4. 8ms symbol parameter test conditions min. typ. max. unit t sd thermal shutdown temperature figure 7 on page 10 140 160 c t hyst thermal shutdown hysteresis figure 7 on page 10 40 c
viper53 - e pin connections and function 7/36 3 pin connections and function figure 1. pin connection (top view) figure 2. current and voltage conventions source tovl comp vdd nc drain source 1 5 4 8 7 6 2 3 osc dip-8 powerso-10 15v vdd osc drain source comp tovl i dd v dd i osc v osc i tovl v tovl i comp v comp i d v d s
pin connections and function viper53 - e 8/36 table 10. pin function pin name pin function v dd power supply of the control circuits. also provides the charging current of the external capacitor during start-up. the functions of this pin are managed by four threshold voltages: - vddon: voltage value at which the device starts switching (typically 11.5 v). - vddoff: voltage value at which the devi ce stops switching (typically 8.4 v). - vddreg: regulation voltage point when working in primary feedback (trimmed to 15 v). - vddovp: triggering voltage of the overvoltage protection (trimmed to 18 v). source power mosfet source and circuit ground reference. drain power mosfet drain. also used by the inte rnal high voltage current source during the start-up phase to charge the external v dd capacitor. comp input of the current mode struct ure, and output of the intern al error amplifier. allows the setting of thedynamic c haracteristic of the converter through an external passive network. the useful voltage range extends fr om 0.5v to 4.5v. the power mosfet is always off below 0.5v, and the overload prot ection is triggered if the voltage exceeds 4.35v. this action is delayed by the timing capacitor connected tothe tovl pin. tovl allows the connection of an external capacitor for delaying the overload protection, which is triggered by a voltage on the comp pin higher than 4.35v. osc allows the setting of the switching fr equency through an external rt-ct network.
viper53 - e operation pictures 9/36 4 operation pictures figure 3. rise and fall time figure 4. overloaded event i d v ds 90% 10% t fv t rv t t 300 v cld c< operation pictures viper53 - e 10/36 figure 5. start-up v dd current figure 6. blanking time figure 7. thermal shutdown figure 8. overvoltage event i dd v dd v ddhyst v ddoff v ddon i dd0 i ddch1 i ddch2 v ds = 100 v f sw = 0 khz t b t b1 t b2 v compbl v comphi v dd v comp t j v ddon t sd t sd -t hyst automatic startup abnormal operation v ds v comp v dd v ddovp switching not switching
viper53 - e operation pictures 11/36 figure 9. shutdown action figure 10. comp pin gain and offset figure 11. output characteristics t t i d v comp t v osc v compoff v oschi v osclo v comp i dpeak v compos v comphi slope = 1 / h comp i dlim v compovl i dmax i comp v dd v ddreg i comphi i complo 0 slope = gm
operation pictures viper53 - e 12/36 figure 12. oscillator schematic the switching frequency settings shown on the graphic here below is valid within the following boundaries: r t > 2k ? f sw = 300khz figure 13. oscillator settings 320 ? source osc vdd pwm section ct rt vcc 110100 10 300 100 frequency (khz) r t (k ? ) 1nf 2.2nf 4.7nf 10nf 22nf
viper53 - e operation pictures 13/36 figure 14. error amplifier test cpfiguration this configuration is for test purpose only. in order to insure a correct stability of the error amplifier, a capacitor of 10nf (minimum value: 8nf) should be always connected between comp pin and ground. see figures figure 18 , 19 and 22 . figure 15. error amplifier transfer function 15v vdd osc drain source comp tovl r 2.5 v vin vout -60 -40 -20 0 20 40 60 gain (db) frequency (hz) open r = 10 k ? r = 2.2 k ? r = 470 ? 1 10 100 1k 10k 100k 1m 10m
operation pictures viper53 - e 14/36 figure 16. typical frequency variation vs. junction temperature figure 17. typical current limitation vs. junction temperature -20 0 20 40 60 80 100 120 0.96 0.98 1 1.02 1.04 normalised frequency temperature (c) -20 0 20 40 60 80 100 120 0.96 0.98 1 1.02 1.04 normalised idlim temperature (c)
viper53 - e primary regula tion configuration example 15/36 5 primary regulation configuration example figure 18. off line power supply with auxiliary supply feedback the schematic on figure 18 delivers a fixed output voltage by using the internal error amplifier of the device in a primary feedback configuration. the prim ary auxiliary winding provides a voltage to the v dd pin, and is automatically regulated at 15v, due to the internal error amplifier connected to this pin. the secondary voltage has to be adjusted through the turn ratio of the transformer between auxiliary and secondary. the error amplifier of the viper53 is a transconductance type: its output is a current proportional to the difference of voltage between the v dd pin and the internally trimmed 15v reference (i.e., the error voltage). as the transconductance value is set at a relatively low value to control the overall loop gain and ensure stability, this cu rrent has to be integrated by a capacitor (c7 in figure 18 ). when the steady state operation is reached, this capacitor blocks any dc current from the comp pin and imposes a ?nil? error voltage. therefore, the v dd voltage is accurately regulated to 15v. this results in a good load regulation, which depends only on transformer coupling and output diodes impedance. the current mode structure takes care of all incoming voltage changes, thus providing at the same time an excellent line regulation. 15v vdd osc drain source comp tov l u1 viper73 r3 r4 d3 d1 c1 t1 c2 f1 r1 d2 c7 c5 c4 c6 t2 d4 c8 c10 l1 c9 r2 c3 ac in dc out c11 10nf r5 r6 1k
primary regulation configuration example viper53 - e 16/36 the switching frequency can be set to any value through the choice of r3 and c5. this allows to optimize the efficiency of the converter by adopting the best compromise between switching losses, emi (lower wit h low switching frequencies) and transformer size (smaller with high switching frequencies). for an output power of a few watts, typical switching frequencies between 20khz and 40khz because of the small size of the transformer. for higher power, 70khz to 130khz are generally chosen. the r5 compensation resistor value sets the dynamic behavior of the converter. it can be adjusted to provide the best compromise between stability and recovery time with fast load changes.
viper53 - e secondary feedback configuration example 17/36 6 secondary feedback configuration example when a more accurate output voltage is needed, the way is to monitor it directly secondary side, and drive the pwm controller through an optocoupler as shown on figure 17. the optocoupler is connected in parallel with the compensation network on the comp pin. the design of the auxiliary wind ing that the vdd voltage is al ways lower than the internal 15v reference. the internal error amplifier will therefore be saturated in the high state, and because of its transconductance nature, will deliver a constant biasing current of 0.6ma to the optotransistor. this current does not depend on the compensation voltage, and so it does not depend on the output load either. consequently, the gain of the optocoupler ensures consequently a constant biasing of the tl431 device (u3) which is in charge of secondary regulation. if the optocoupler gain is sufficiently low, no additional components are required to ensure a minimum current biasing of u3. also, the low biasing current value avoid any ageing of the optocoupler. the constant current biasing can be used to simplify the secondary circuit: instead of a tl431, a simple zener and resistance network in series with the optocoupler diode can insure a good secondary regulation. as the current flowing in this branch remains constant for the same reason as above, typical load regulation of 1% can be achieved from zero to full output current with this simple configuration. figure 19. off line power supply with optocoupler feedback 15v vd d osc drain source comp tovl u1 vipe r7 3 r5 r3 r4 d3 d1 c1 t1 c2 f1 r1 d2 c7 c5 c4 c6 t2 d4 c8 c10 l1 c9 r2 c3 ac in dc out u2 u3 c12 r6 r7 r8 c11 10nf r9 1k
secondary feedback configuration example viper53 - e 18/36 since the dynamic characteristics of the converter are set on the secondary side through components associated to u3, the compensation network has only a role of gain stabilization for the optocou pler, and its value can be freely chosen. r5 can be set to a fixed value of 1k ? , offering the possibility of using c7 as a soft start capacitor: when starting up the converter, the viper53 device delivers a constant current of 0.6 ma on the comp pin, creating a constant voltage of 0.6v in r5 and a rising slope across c7. this voltage shape, together with the operating range of 0.5v to 4.5v provides a soft start-up of the converter. the rising speed of the output voltage can be set through the value of c7. the c4 and c6 values must be adjusted accordingly in order to ensure a correct start-up.
viper53 - e current mode topology 19/36 7 current mode topology the VIPER53-E implements the conventional current mode control method for regulating the output voltage. this kind of feedback includes two nested regulation loops: the inner loop controls the peak primary current cycle by cycle. when the power mosfet output transistor is on, the inductor current (primary side of the transformer) is monitored with a sensefet technique and converted into a voltage. when v s reaches v comp , the power switch is turned off. this structure is completely integrated as shown on the block diagram on page 1 , with the current amplifier, the pwm comparator, the blanking time function and the pwm latch. the following formula gives the peak current in the power mosfet according to the compensation voltage: equation 1 the outer loop defines the level at which the inner loop regulates peak current in the power switch. for this purpose, v comp is driven by the feedback network (tl431 through an optocoupler in secondary feedback configuration, see figure 19 on page 17 ) and is sets accordingly the peak drain current for each switching cycle. as the inner loop regulates the peak primary current in the primary side of the transformer, all input voltage changes are compensated for before impacting the output voltage. this results in an improved line regulation, instantaneous correction to line changes, and better stability for the volt age regulation loop. current mode topology also provides a good converter start-up control. the compensation voltage can be controlled to increase slowly during the start-up phase, so the peak primary current will follow this soft voltag e slope to provide a smooth out put voltage rise, without any overshoot. the simpler voltage mode structure which only controls the duty cycle, leads generally to high current at start-up with the risk of transformer saturation. an integrated blanking filter inhibits the pwm comparator output for a short time after the integrated power mosfet is switched on. this function prevents anomalous or premature termination of the switching pu lse in the case of current sp ikes caused by primary side transformer capacitance or secondary side rectifier reverse recovery time when working in continuous mode. i dpeak v comp v compos ? h comp ------------------------------------------------- - =
standby mode viper53 - e 20/36 8 standby mode the device offers a special feature to address the low load condition. the corresponding function described hereafter consists of reduci ng the switching frequency by going into burst mode, with the following benefits: ? it reduces the switching losses, thus providing low consumption on the mains lines. the device is compliant with ?blue angel? and other similar standards, requiring less than 0.5 w of input power when in standby. ? it allows the regulation of the output voltage, even if the load corresponds to a duty cycle that the device is not able to generate because of the internal blanking time, and associated minimum turn on. for this purpose, a comparator monitores the comp pin voltage, and maintains the pwm latch and the power mosfet in the off state as long as v comp remains below 0.5v (see block diagram on page 1 ). if the output load requires a duty cycle below the one defined by the minimum turn on of the device, the v comp net decreases its voltage until it reaches this 0.5v threshold (v compoff ). the power mosfet can be comp letely off for some cycles, and resumes normal operation as soon as v comp is higher than 0.5v. the output voltage is regulated in burst mode. the corresponding ripple is not higher than the nominal one at full load. in addition, the minimum turn on time which defines the frontier between normal operation and burst mode changes according to v comp value. below 1.0v (v compbl ), the blanking time increases to 400ns, whereas for higher voltages, it is 150ns figure 6 on page 10 the minimum turn on times resulting from these values are respectively 600 ns and 350 ns, when taking into account internal propagation time. this brutal change induces an hysteresis between normal operation and burst mode as shown on figure 20 on page 21 . when the output power decreases, the system reaches point 2 where v comp equals v compbl . the minimum turn-on time passes immediately from 350ns to 600ns, exceeding the effective turn-on time that should be needed at this output power level. therefore the regulation loop will quickly drive v comp to v compoff (point 3) in order to pass into burst mode and to control the output voltage. the corresponding hysteresis can be seen on the switching frequency which passes from f swnom which is the normal switching frequency set by the components connected to the osc pin and to fswstby. note: this frequency is actually an equivalent number of switching pulses per second, rather than a fixed switching frequency since the device is working in burst mode. as long as the power remains below p rst the output of the regulation loop remains stuck at v compsd and the converter works in burst mode. its ?density? increases (i.e. the number of missing cycles decreases) as the power approaches p rst and finally resumes normal operation at point 1. the hysteresis cannot be seen on the switching frequency, but it can be seen in the sudden surge of the comp pin voltage from point 3 to point 1 at that power level. the power points value p rst and p stby are defined by the following formulas: equation 2 p rst 1 2 -- - f swnom ? tb 1 td + () ? 2 v 2 ? in 1 lp ------ - ? =
viper53 - e standby mode 21/36 equation 3 where ip(v compbl 2 ) is the peak power mosfet current corresponding to a compensation voltage of v compbl (1v). note: the power point pstby where the converter is going into burst mode does not depend on the input voltage. the standby frequency f swstby is given by: equation 4 the ratio between the nominal and standby switching frequencies can be as high as 4, depending on the lp value and input voltage. figure 20. standby mode implementation p stby 1 2 -- - f swnom ? ip 2 v compbl () ? lp ? = p swstby p stby p rst ----------------- f swnom ? = v comp v compsd v compbl v compoff 600ns 350ns f sw p in f swnom f swstby p stby p rst minimum 1 3 2 1 2 3 ton turn on
high voltage start-up current source viper53 - e 22/36 9 high voltage start-up current source an integrated high voltage current source provides a bias current from the drain pin during the start-up phase. this current is partially absorbed by internal control circuits in standby mode with reduced consumption, and also supplies the external capacitor connected to the v dd pin. as soon as the voltage on this pin reaches the high voltage threshold v ddon of the uvlo logic, the device turns into active mode and starts switching. the start-up current generator is switched off, and the converter should normally provide the needed current on the v dd pin through the auxiliary winding of the transformer, as shown on figure 19 on page 17 . the external capacitor c vdd on the v dd pin must be sized according to the time needed by the converter to start-up, when the device starts switching. this time tss depends on many parameters, including transformer design, output capacitors, soft start feature, and compensation network implemented on the comp pin and possible secondary feedback circuit. the following formula can be used for defining the minimum capacitor needed: equation 5 figure 21 on page 23 shows a typical start-up event. v dd starts from 0v with a charging current i ddch1 at about 9 ma. when about v ddoff is reached, the charging current is reduced down to i ddch2 which is about 0.6ma. this lower current leads to a slope change on the v dd rise. device starts switching for v dd equal to v ddon , and the auxiliary win ding delivers some energy to v dd capacitor after the start-up time tss. the charging current change at v ddoff allows a fast complete start-up time t sdu , and maintains a low restart duty cycle. this is espe cially useful for short circuits and overloads conditions, as described in the following section. c vdd i dd1 tss ? v ddhyst --------------------------- >
viper53 - e high voltage start-up current source 23/36 figure 21. start-up waveforms i dd i dd1 tss i ddch2 i ddch1 t t v ddsd v ddst v ddreg v dd tsu
short-circuit and overload protection viper53 - e 24/36 10 short-circuit and overload protection a v compovl threshold of about 4.35v has been implemented on the comp pin. when v comp goes above this level, the capacitor conn ected on the tovl pin begins to charge. when reaching typically v ovlth (4v), the internal mosfet driver is disabled and the device stops switching. this state is latched because of to the regulation loop which maintains the comp pin voltage above the v compovl threshold. since the v dd pin does not receive any more energy from the auxiliary winding, it s voltage drops down until it reaches v ddoff and the device is reset, recharging the v dd capacitor for a new restart cycle. note: if vcomp drops below the v compovl threshold for any reason during the vdd drop, the device resumes switching immediately. the device enters an endless restart sequence if the overload or short circuit condition is maintained. the restart duty cycle d rst is defined as the time ratio for which the device tries to restart, thus delivering its full power capab ility to the output. in order to keep the whole converter in a safe state during this event, d rst must be kept as low as possible, without compromising the real start-up of the converter. a typical value of about 10% is generally sufficient. for this purpose, both v dd and tovl capacitors can be used to satisfy the following conditions: equation 6 equation 7 refer to the previous start-up section for the definition of tss, and c vdd must also be checked against the limit given in this sectio n. the maximum value of the two calculus will be adopted. all this behavior can be observed on figure 8 on page 10 . in figure 10 on page 11 the value of the drain current id for v comp = v compovl is shown. the corresponding parameter i dmax is the drain current to take into account for design purposes. since i dmax represents the maximum value for which the overload protection is not triggered, it defines the power capability of the power supply. c ovl 12.5 10 6 ? tss ?? > c vdd 810 4 1 d rst -------------- 1 ? ?? ?? c ovl i ddch2 ? v ddhyst --------------------------------------- ?? ? >
viper53 - e transconductance error amplifier 25/36 11 transconductance error amplifier the VIPER53-E includes a transconductance error amplifier. transconductance gm is the change in output current i comp versus change in input voltage v dd . thus: equation 8 the output impedance z comp at the output of this amplifier (comp pin) can be defined as: equation 9 this last equation shows that the open loop gain a vol can be related to gm and z comp : equation 10 where gm value for viper5 3 is typically 1.4ma/v. gm is well defined by specification, but z comp, and therefore a vol, are subject to large tolerances. an impedance z must be connected between the comp pin and ground in order to accurately define the transfer function f of the error amplifier, the following equation, very similar to the one above: equation 11 the error amplifier frequency response is shown in .0 for different values of a simple resistance connected on the comp pin. the unloaded transconductance error amplifier shows an internal z comp of about 140k ? . more complex impedances can be connected on the comp pin to achieve different compensation methods. a capacitor provides an integrator function, thus eliminating the dc static error, and a resistance in series leads to a flat gain at higher frequency, introducing a zero level and ensuring a correct phase margin. this configuration illustrated in figure 22 , for the schematic and figure 23 on page 28 for the error amplifier transfer function for a typical set of values of c comp and r comp . note that a 10nf capacitor (8nf, minimum value) should always be connected to the comp pin to ensure a correct stability of the internal error amplifier. the complete converter open loop transfer function can be built from both power cell and error amplifier transfer functions. a theoretical example can be seen in figure 24 for a discontinuous mode flyback loaded by a simple resistor, regulated from primary side (no gm ? i comp ? v dd ------------------- - = z comp ? v comp ? i comp --------------------- - 1 gm --------- - ? v comp ? v dd --------------------- - ? = = a vol gm z comp ? = fs () gm z s () ? =
transconductance error amplifier viper53 - e 26/36 optocoupler, the internal error amplifier is fully used for r egulation). a typical schematic corresponding to this situation can be seen on figure 18 . the transfer function of the power cell is represented as g(s) in figure 24 iexhibits a pole which depends on the output load and on the output capacitor value. as the load of a converter may change, two curves are shown for two different values of output resistance value, r l1 and r l2 . a zero at higher frequency values then appears, due to the output capacitor esr. note: the overall transfer function does not depend on the input voltage because of the current mode control. the error amplifier has a fixed behavior, similar to the one shown in figure 23 . its bandwidth is to avoid injection of high frequency noise in the current mode section. a zero due to the r comp -c comp network is set at the same value as the maximum load r l2 pole. the total transfer function is shown as f(s). g(s) at the bottom of figure 24 . for maximum load (plain line), the load pole is exactly compensated by the zero of the error amplifier, and the result is a perfect first order decreasing until it reaches the zero of the output capacitor esr. the error amplifier cut-off then definitely any further spurious noise or resonance from disturbing the regulation loop. the point where the complete transfer function has a unity gain is known as the regulation bandwidth and has: ? the higher it is, the faster the reaction will be to an ev entual load change, and the smaller the output vo ltage change will be. ? the phase shift in the complete system at this point has to be less than 135 to ensure good stability. generally, a first-orde r slope gives 90 of phase shift, and a second-order gives 180. in figure 24 , the unity gain is reached in a first order slope, so the stability is ensured. the dynamic load regulation is improved by increasing the regulation bandwidth, but some limitations have to be respected: as the transfer function above the zero due the capacitor esr is not reliable (the esr itse lf is not well specified, and other parasitic effects may take place), the bandwidth should always be lower than the minimum of f c and esr zero. as the highest bandwidth is obtained with the highest output power (plain line with r l2 load in figure 24 ), the above criteria will be checked for this condition and a llows to define the value of r comp , as the error amplifier gain depends only on this value for this frequency range. the following formula can be derived: equation 12 r comp p out2 p max ----------------- f bw2 r l2 c out ?? gm ------------------------------------------------------ ? = p out2 v out 2 r l2 -------------- = p max 1 2 -- - l p i lim 2 f sw ?? ? = with: and:
viper53 - e transconductance error amplifier 27/36 the lowest load gives another cond ition for stability: the frequency f bw1 must not encounter the second order slope generated by the load pole and the integrator part of the error amplifier. this condition ca n be met by adjusting the c comp value: equation 13 the above formula gives a minimum value for c comp . it can be then increased to provide a natural soft start function as this capacitor is charged by the error amplifier current capacity i comphi at start-up. figure 22. typical compensation network c comp r l1 c out ? 6.3 gm r comp 2 ?? ----------------------------------------------------- - p out1 p max ------------------ - ? > p out1 v out 2 r l1 --------------- = with: 15v vdd osc drain source comp tovl rcomp ccomp 10nf
transconductance error amplifier viper53 - e 28/36 figure 23. typical transfer functions frequency (hz) 1 10 100 1k 10k 100k 1m gain (db) -10 0 10 20 30 40 50 60 rcomp=4.7k ccomp=470nf frequency (hz) phase () 1 10 100 1k 10k 100k 1m -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 rcomp=4.7k ccomp=470nf
viper53 - e transconductance error amplifier 29/36 figure 24. complete converter transfer function g(s) f f c f f f(s) f(s).g(s) 1 r l1 c out ?? ----------------------------------------------- 1 r l2 c out ?? ----------------------------------------------- 1 2 esr c out ?? ? ----------------------------------------------------------- 1 2 r comp c comp ?? ? --------------------------------------------------------------------------- - f bw 2 f bw 1 1 1 1
special recommendations viper53 - e 30/36 12 special recommendations as steted in the error amplifier section, a capacitor of 10nf capacitor (minimum value: 8nf) should always be connected to the comp pin to ensure correct stability of the internal error amplifier figure 18 , 19 and 22 . in order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1k ? should be inserted in series with the tovl pin, as shown on figure 18 , figure 19 on page 17 . note that, this resistance does not impact the ov erload delay, as its value is negligible prior to the internal pull-up resistance (about 125k ? ). 13 software implementation all the above considerations and some others are included included in st design software which provides all of the needed components around the viper device for specified output configurations, and is available on www.st.com.
viper53 - e package mechanical data 31/36 14 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com .
package mechanical data viper53 - e 32/36 figure 25. package dimensions table 11. dip8 mechanical data dimensions ref. databook (mm) nom. min max a 5.33 a1 0.38 a2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 d 9.02 9.27 10.16 e 7.62 7.87 8.26 e1 6.10 6.35 7.11 e2.54 ea 7.62 eb 10.92 l 2.92 3.30 3.81 package weight gr. 470
viper53 - e package mechanical data 33/36 figure 26. package dimensions table 12. powerso-10 mechanical data dimensions ref. databook (mm) nom. min max a 3.35 3.65 a1 0.00 0.10 b 0.40 0.60 c 0.35 0.55 d 9.40 9.60 d1 7.40 7.60 e 9.30 9.50 e1 7.20 7.40 e2 7.20 7.60 e3 6.10 6.35 e4 5.90 6.10 e 1.27 f 1.25 1.35 h 13.80 14.40 h 0.50 l 1.20 1.80 q 1.70 0 8
order codes viper53 - e 34/36 15 order codes table 13. order codes part number package shipment viper53dip-e dip-8 tube viper53sp-e powerso-10 tube viper53sptr - e powerso-10 tape and reel
viper53 - e revision history 35/36 16 revision history table 14. revision history date revision changes 13-nov-2006 1 initial release.
viper53 - e 36/36 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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